In recent years, high integration and high density in semiconductor device demands miniaturization of wiring patterns or interconnections and also increase of the number of interconnection layers in the device. The trend for the device having multilayered interconnections in smaller circuits generally widens the width of steps due to the surface irregularities on lower interconnection layers, resulting in degradation of flatness. An increase in the number of interconnection layers could worsen a quality of film coating (step coverage) over stepped configurations in the process of forming thin films. In summary, firstly, the advent of highly-layered multilayer interconnections necessitates the new planarization process capable of attaining improved step coverage and proper surface accordingly. Secondly, this trend and another reason as described below need a new process capable of planarizing a surface of the semiconductor device: a surface of the semiconductor device needs to be planarized such that irregular steps on the surface of the semiconductor device will fall within the depth of focus. Therefore, the smaller the depth of focus of a photolithographic optical system with miniaturization of a photolithographic process becomes, the more precisely flattened surface after planarization process is needed.
Thus, in a manufacturing process of a semiconductor device, it increasingly becomes important to planarize a surface of the semiconductor device. One of the most important planarizing technologies is chemical mechanical polishing (CMP). Thus, there has been employed a chemical mechanical polishing apparatus for planarizing a surface of a semiconductor wafer. In the chemical mechanical polishing apparatus, while a polishing liquid containing abrasive particles such as silica (SiO2) therein is supplied onto a polishing surface such as a polishing pad, a substrate such as a semiconductor wafer is brought into sliding contact with the polishing surface, so that the substrate is polished.
This type of polishing apparatus includes a polishing table having a polishing surface formed by a polishing pad, and a substrate holding apparatus, which is referred to as a top ring or a polishing head, for holding a substrate such as a semiconductor wafer. When a semiconductor wafer is polished with such a polishing apparatus, the semiconductor wafer is held and pressed against the polishing surface of the polishing pad under a predetermined pressure by the substrate holding apparatus. At this time, the polishing table and the substrate holding apparatus are moved relative to each other to bring the semiconductor wafer into sliding contact with the polishing surface, so that the surface of the semiconductor wafer is polished to a flat mirror finish.
Conventionally, as a substrate holding apparatus, there has been widely used a so-called floating-type top ring in which an elastic membrane (membrane) is fixed to a chucking plate, and a fluid such as air is supplied to a pressure chamber (pressurizing chamber) formed above the chucking plate and a pressure chamber formed by the elastic membrane (membrane) to press a semiconductor wafer against a polishing pad under a fluid pressure through the elastic membrane. In the floating-type top ring, the chucking plate is floated by a balance between a pressure of the pressurizing chamber above the chucking plate and a pressure of the membrane below the chucking plate so as to press the substrate onto the polishing surface in an appropriate pressing force, thereby polishing the semiconductor wafer. In this top ring, when application of the pressure to the semiconductor wafer is started or vacuum-chucking of the semiconductor wafer is performed after polishing, the following operation is carried out:
When application of the pressure to the semiconductor wafer is started, the pressurizing chamber is pressurized, the chucking plate which holds the semiconductor wafer by the membrane is lowered to bring the polishing pad, the semiconductor wafer and the membrane into close contact with each other. Then, a desired pressure is applied to the membrane, and thereafter or simultaneously, the pressure of the pressurizing chamber is regulated to be not greater than the membrane pressure, thereby allowing the chucking plate to float. In this state, the semiconductor wafer is polished. In this case, the reason why the chucking plate is first lowered to bring the polishing pad, the semiconductor wafer and the membrane into close contact with each other is that a pressurized fluid between the semiconductor wafer and the membrane should be prevented from leaking. If pressure is applied to the membrane in a state in which the polishing pad, the semiconductor wafer and the membrane are not brought into close contact with each other, a gap is produced between the semiconductor wafer and the membrane, and the pressurized fluid leaks through the gap.
Further, if the pressure of the pressurizing chamber is not less than the membrane pressure at the time of polishing, the chucking plate presses the semiconductor wafer locally, and a thin film on the semiconductor wafer is polished excessively in local regions thereof. Therefore, the pressure of the pressurizing chamber is regulated to be not more than the membrane pressure, thereby allowing the chucking plate to float. Then, after polishing, at the time of vacuum-chucking of the semiconductor wafer, the pressurizing chamber is pressurized to lower the chucking plate, and the polishing pad, the semiconductor wafer and the membrane are brought into close contact with each other. In this state, the semiconductor wafer is vacuum-chucked to the membrane by creating vacuum above the membrane.
As described above, in the floating-type top ring having the chucking plate, when application of the pressure to the semiconductor wafer is started, or the semiconductor wafer is vacuum-chucked to the membrane after polishing, it is necessary to control a vertical position of the chucking plate by the balance between the pressure of the pressurizing chamber and the membrane pressure. However, in use of this floating-type top ring, because the pressure balance controls the position of the chucking plate, it is difficult to control the vertical position of the chucking plate precisely in the level of required for a recent fabrication process of highly miniaturized and multilayered device. Further, the pressurizing chamber having a large volume requires sufficiently long time when application of the pressure to the semiconductor wafer is started or the semiconductor wafer is vacuum-chucked after polishing due to prolongation of inflation or deflation process of the chamber, and there is a lower limit for a volume of chamber for an appropriated balancing as described above. This is thought to impede an improvement in productivity of the polishing apparatus. Further, in the floating-type top ring, as wear of the retainer ring progresses, the distance between the polishing surface and the lower surface of the chucking plate is shortened, and the amount of expansion and contraction of the membrane in the vertical direction varies locally, thus causing variation of the polishing profile.
Therefore, recently, a top ring which has an improved controllability of a vertical position of a carrier (top ring body), as a supporting member of a membrane, from a polishing surface in precise level has been used as an alternative. A vertical motion of the top ring is usually performed by a servomotor and a ball screw, and thus it is possible to position the carrier (top ring body) instantly at a predetermined height. This shortens a time for an operation in relative to the conventional top ring when application of the pressure to the semiconductor wafer is started or the semiconductor wafer is vacuum-chucked after polishing, and hence it is possible to improve productivity of the polishing apparatus in relative to floating-type top ring. Further, in this top ring, i.e. membrane type top ring, because the vertical position of the carrier from the polishing surface can be controlled precisely, the polishing profile of the edge portion of the semiconductor wafer can be adjusted not by balancing such as floating-type top ring but by regulating the expansion of the membrane. Further, since the retainer ring can be moved vertically independently of the carrier, even if the retainer ring is worn, the vertical position of the carrier from the polishing surface is not affected. Accordingly, lifetime of the retainer ring can be prolonged dramatically.
In this type of top ring, when application of the pressure to the semiconductor wafer is started or the semiconductor wafer is vacuum-chucked after polishing, the following operation is normally performed:
When application of the pressure to the semiconductor wafer is started, the carrier, or top ring which holds the semiconductor wafer under vacuum by the membrane is lowered onto the polishing pad. At this time, the top ring is moved to the height where a desired polishing profile can be obtained in the subsequent polishing process. Normally, in the membrane-type top ring having good elasticity, since the peripheral portion (edge portion) of the semiconductor wafer is liable to be polished, it is desirable that the pressure applied to the semiconductor wafer should be reduced by a loss caused by expansion of the membrane by raising the height of the top ring. Specifically, the top ring is lowered to the height where the gap between the semiconductor wafer and the polishing pad is about 1 mm, typically. Thereafter, the semiconductor wafer is pressed against the polishing surface and is polished. After polishing, the semiconductor wafer is vacuum-chucked to the top ring while the top ring remains the same height as that of polishing. However, the conventional polishing method thus conducted has the following problems unforeseen at first.
A gap between the semiconductor wafer and the polishing pad when application of the pressure to the semiconductor wafer is started may result in deformation of the semiconductor wafer. This deformation could be reached to a large degree, in proportion to a quantity corresponding to the gap between the semiconductor wafer and the polishing pad. Therefore, stress applied to the semiconductor wafer increases in such case, resulting in increase of breakage of fine interconnections formed on the semiconductor wafer or damage of the semiconductor wafer itself. On the other hand, when the semiconductor wafer is vacuum-chucked after polishing, if the semiconductor wafer is attached to the carrier by creating vacuum above the membrane from the state in which there is a gap between the lower surface of the carrier and the upper surface of the membrane, then the deformation quantity of the semiconductor wafer becomes larger by a quantity corresponding to the gap between the lower surface of the carrier and the upper surface of the membrane. Therefore, stress applied to the semiconductor wafer increases and the semiconductor wafer is damaged in some cases in operation of membrane-type top ring. However, a challenge to avoid such defect has not been successful so far. Firstly, to form no gap is not successful: when pressure is applied to the semiconductor wafer or the semiconductor wafer is vacuum-chucked, if the top ring is lowered to the position where there is almost no gap between the semiconductor wafer and the polishing pad or the semiconductor wafer is brought into contact with the polishing pad locally, then a thin film on the semiconductor wafer is polished excessively or the semiconductor wafer itself is damaged at the worst.
Secondly, a release nozzle disclosed in Japanese laid-open patent publication No. 2005-123485, having been used to reduce stress applied to the semiconductor wafer when the semiconductor wafer is released from the top ring, can be thought to be alternative. The release nozzle serves as an assisting mechanism for assisting the release of the semiconductor wafer from the top ring by ejecting a pressurized fluid between the rear surface of the semiconductor wafer and the membrane. In this case, the semiconductor wafer is pushed out downwardly from the bottom surface of the retainer ring to remove the peripheral portion of the semiconductor wafer from the membrane, and then the pressurized fluid is ejected between the peripheral portion of the semiconductor wafer and the membrane. Therefore, when the semiconductor wafer is released from the top ring, it is necessary to inflate the membrane by pressuring the membrane, as seen in Japanese laid-open patent publication No. 2005-123485. The release nozzle is also disclosed in U.S. Pat. No. 7,044,832. As disclosed in this U.S. patent publication, when the semiconductor wafer is released, the bladder is inflated (pressurized), and then a shower is sprayed in a state in which the edge portion of the semiconductor wafer is separated from the bladder (see the 6th to 15th lines of the column 10 and FIG. 2A). Specifically, in both of the above publications, the membrane is inflated to separate the edge portion of the semiconductor wafer from the membrane, and a shower is sprayed into the gap. However, when the membrane in these publications is pressurized and inflated as suggested, locally varied downforce is applied to the substrate. Accordingly, stress tends to be applied to the semiconductor wafer locally in accordance with inflation of membrane, and fine interconnections formed on the semiconductor wafer are broken or the semiconductor wafer itself is damaged at the worst in use of these conventional top rings having nozzle. There needs a planarization process for attaining both of precise flatness and high-throughput, with reduced defect of a substrate due to the planarization process.